Network devices may adopt Ethernet bus architecture. In the Ethernet bus architecture, the network device may include a mainboard and an interface board, a first Ethernet data channel is formed between a CPU of a mainboard and an Ethernet switch chip of the mainboard, a second Ethernet data channel is formed between the Ethernet switch chip of the mainboard and a logic apparatus of an interface board, and an interface data channel is formed between the logic apparatus of the interface board and an interface chip of the interface board. The bandwidth of the first Ethernet data channel may not match with the bandwidth of the second Ethernet data channel, and the bandwidth of the second Ethernet data channel may not match with the bandwidth of the interface data channel.
Thus, congestion of data packets may occur frequently in an egress direction. This can make it hard for the network device to accurately implement Quality of Service (QOS) in the egress direction.